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@anangl anangl commented Oct 20, 2025

This is a follow-up to commit f0f5f8c.

There is no need to check if TXE interrupt flag is set before calling tx_dummy_bytes(), as the function can handle the case when it is called even though there is no room in the TX FIFO. On the other hand, the check may be actually harmful, as it may prevent adding more items to the TX FIFO while the SSI controller is waiting until the FIFO achieves its transfer start level. Remove the check then and exit the ISR loop when no dummy bytes could be written into the TX FIFO.

(cherry picked from commit 7ff2be0)

This is a follow-up to commit f0f5f8c.

There is no need to check if TXE interrupt flag is set before
calling tx_dummy_bytes(), as the function can handle the case
when it is called even though there is no room in the TX FIFO.
On the other hand, the check may be actually harmful, as it may
prevent adding more items to the TX FIFO while the SSI controller
is waiting until the FIFO achieves its transfer start level.
Remove the check then and exit the ISR loop when no dummy bytes
could be written into the TX FIFO.

Signed-off-by: Andrzej Głąbek <[email protected]>
(cherry picked from commit 7ff2be0)
@anangl anangl merged commit 3a3b437 into nrfconnect:main Oct 24, 2025
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@anangl anangl deleted the mspi_dw_fix_single_io_rx_isr_follow_up_ncs branch October 24, 2025 06:38
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3 participants